This invention relates to a metal gate complementary metal oxide semiconductor (CMOS) and a method of manufacturing the same, and, more particularly, to a robust metal gate CMOS having no silicon facet at the active silicon to shallow trench isolation (STI) interface, and a method of fabricating such a device.
Conventional metal gate complementary metal oxide semiconductor (CMOS) devices are processed using multiple fabrication steps such as, for example, nitride deposition and etching steps, oxide deposition and etching steps, and planarization steps. With each additional step of the process, the overall yield of the process is potentially decreased. Accordingly, there is a need to reduce the number of required processing steps in order to improve the yield of the overall fabrication process.
U.S. Pat. No. 6,200,866 B1 to Ma et al. discloses a process of using silicon germanium and other alloys as the replacement gate for the fabrication of a metal oxide semiconductor field effect transistor (MOSFET). The method discloses the steps of depositing a silicon germanium layer over the source, drain and gate regions. The silicon germanium over the source and drain regions is then etched to leave a silicon germanium island in the gate region, with exposed source and drain regions. The source and drain regions are then fabricated by a doping process or the like. Oxide spacers are then formed around the gate island, a polysilicon layer deposited over the source, drain and gate regions, and then chemical mechanical polishing is conducted to planarize the device. The dummy gate material is then removed and the gate dielectric and gate electrode materials are deposited.
Due to the formation of the shallow trench isolation early in the process, throughout the subsequent oxide/nitride pad etching process steps, the resulting device typically will include some silicon faceting at the active silicon to shallow trench isolation interface. In particular, as shown in FIG. 12, the silicon faceting comprises a wedge shaped gap in the shallow trench region, directly adjacent to the active region of the device. This silicon faceting often results in a corner transition effect that renders the device unreliable.
Accordingly, there is a need for a device that has reduced silicon faceting at the active silicon-to-shallow-trench-isolation-interface and that has reduced corner transition effects. Moreover, there is a need for a device fabrication process that has a reduced number of steps so as to potentially improve the overall yield of the process.
The present invention provides a robust metal gate CMOS having no silicon facet at the active silicon to shallow trench insolation (STI) interface. The device is manufactured by a process that is more simple than prior art fabrication processes because the present invention eliminates a nitride etch step, an oxide etch step and an oxidation process step from a known fabrication process. The process also provides self-aligned planarization stops to provide for better planarization of the device. The fabricated device, having no silicon facet at the active silicon to STI interface, provides a more reliable gate oxide and eliminates the corner transition effect.
Accordingly, an object of the invention is to provide a simpler and more robust metal gate CMOS device and a method of fabricating the same.
Another object of the invention is to provide a method that eliminates a nitride etch step, an oxide etch step, and an oxidation process step from a previously known process.
A further object of the invention is to provide a device having better planarization capabilities and no silicon facet at the active silicon to STI interface area.
Yet a further object of the invention is to provide a device that includes a more reliable gate oxide that reduces or eliminates the corner transistor effect.